In multi-bank memory systems, a memory controller connects to a memory device and a microprocessor. A microprocessor sends requests to the memory controller and a memory controller processes requests to access a bank storing data in a memory device. In this way, a memory controller acts as a liaison between a microprocessor and a memory device.
A memory controller may connect with multiple microprocessors and multiple memory devices. Likewise, a microprocessor may connect with multiple memory controllers. For example, a memory controller can connect to one or more dual in-line memory modules (DIMMs) via a set of buses and each DIMM can contain multiple dynamic random access memory (DRAM) devices. In some devices, a microprocessor couples to multiple memory controllers and each memory controller couples to multiple memory devices. A memory controller manages each memory device coupled to the memory controller.
Many memory devices, such as a DRAM device, contain one or more arrays of storage elements organized into ranks, banks, pages, rows and columns. Each rank of memory is a set of one or more DRAM devices that operate in lockstep in response to a command. A bank is a number of independent DRAM arrays within a DRAM device. Thus, each rank can comprise a number of banks and each bank can contain a number of pages. At the lowest level, pages are organized in rows and columns.
Every access to memory uses a certain amount of power and time or latency. Upon receiving a request, a corresponding rank and bank must be determined. From there, the row and certain columns within the bank are selected to perform a read or write operation. To access a memory device, memory controllers process an address of memory to identify the rank, bank, page, row and column of an appropriate memory device. Once identified, a bank must be opened, or pre-charged, and page must be activated before data is sent or received into memory.
Additionally, memory controllers send data and commands to memory devices via bus lines. Bus lines are also used to carry information in response to commands back to a memory controller. Generally, the full width of a bus line is not consistently used during memory accesses.
In the past, read and write operations in typical memories took place only on the rising or falling edge of a clock signal. Today, many devices utilize double data rate (DDR) memories. DDR memories are read and written both on rising edges and on falling edges of a clock signal. This allows DDR memories to double the data rate.